Semiconductor integrated circuits are becoming increasingly complex, yet there is a constant drive to decrease the size of the circuits. The drive to decrease the size and increase the density of these circuits can result in several problems which may cause circuit failures if they are not addressed. Latch-up is one problem which can occur frequently in densely packed devices if not properly addressed. Latch-up can be triggered by many mechanisms and can cause the circuit to fail. Latch-up is commonly caused by the close proximity of n-type and p-type devices in CMOS circuits, where the parasitic NPN bipolar transistors can be triggered into a low resistance holding state. This low resistance state can draw large currents which can be destructive.
STI is commonly used to isolate n-channel and p-channel devices in CMOS circuits. STI reduces the likelihood of latch-up, among other advantages. However, as semiconductor devices become smaller and more densely packed, certain features of the device also become smaller, while other features remain constant:. For example, the n+ and p+ space, as well as the STI trench depth has scaled smaller, while EPI thickness has remained constant.
The EPI thickness needs to remain constant in order to accommodate retrograde wells. A retrograde well is one in which the surface doping is lower than the doping of the well deeper into the substrate, that is, the further in the substrate, the higher the doping concentration. Hence, a retrograde well requires a fairly thick EPI to accommodate the deeper retrograde wells.
The STI depth is required to be deep enough to adequately isolate devices. As the STI width is scaled smaller, higher aspect ratio trenches are formed that are difficult to fill. When a trench with a high aspect ratio is filled, voids are often created in the fill which may cause a variety of problems. Additionally, as the size of the STI is reduced, latch-up immunity is decreased. Therefore, there is a need for an isolation structure which is easy to manufacture and which also improves the latch-up of densely packed semiconductor devices.